EDA

Electronic Design Automation market has a value of around US$6B. It enables the full semiconductor market which is at US$621B today.

Today the Electronic Design Automation market is dominated by three players, two of which are covering the full IC Design flow: Cadence and Synopsys. Mentor Graphics, now part of Siemens, is the third player with the de facto standard for the IC backend verification flow. Whereas in the old days new entrants were already rare (Magma Design Automation being the last entrant with an almost complete flow) today it is virtually impossible to build a complete flow from scratch. Today’s innovations are in the specific parts of the (system) design covering such areas as HW/SW co-design, 3D packaging and specific target synthesis tools. In general. the existing flows require a high degree of “maintenance” to keep up with the technology changes and the reduced margins coming with ever high speed signals. This impacts anything form power simulation to clock tree buffering and routing. At “the top” there is an urgent need for tools that support accurate and rapid evaluation of the different partitioning options and which one provides the best results based on the target characteristics of the IC (and the product it will live in). Partitioning here relates to the choice between what goes into HW and what is SW-based. Several tools and platforms are trying to address this “top of the iceberg” challenge: the ability to write code and partition it to HW and SW to meet performance characteristics. Specifically, for FPGA platforms there are a few rudimentary tools that attempt to deliver this functionality. However, the state-of-the-art today is not yet from what is required to make it a useful and effective tool as part of the overall design flow.